1. Field of the Invention
This invention relates to error correction in electronic systems and, more particularly, to systems that employ error correction codes to facilitate correction of bit errors due to, for example, component failures.
2. Description of the Related Art
Error codes are commonly used in electronic systems to detect and correct data errors, such as transmission errors or storage errors. For example, error codes may be used to detect and correct errors in data transmitted via a telephone line, a radio transmitter, or a compact disc laser. Error codes may additionally be used to detect and correct errors associated with data stored in the memory of computer systems. One common use of error codes is to detect and correct errors of data transmitted on a data bus of a computer system. In such systems, error correction bits, or check bits, may be generated for the data prior to its transfer or storage. When the data is received or retrieved, the check bits may be used to detect and correct errors within the data.
Component failures are a common source of error in electrical systems. Faulty components may include faulty memory chips or faulty data paths provided between devices of a system. Faulty data paths can result from, for example, faulty pins, faulty data traces, or faulty wires.
Hamming codes are a commonly used type of error code. The check bits in a Hamming code are parity bits for portions of the data bits. Each check bit provides the parity for a unique subset of the data bits. If an error occurs (i.e. one or more of the data bits change state), one or more of the check bits upon regeneration will also change state (assuming the error is within the class of errors covered by the code). By determining the specific bits of the regenerated check bits that changed state, the location of the error within the data may be determined. For example, if one data bit changes state, this data bit will cause one or more of the regenerated check bits to change state. Because each data bit contributes to a unique group of check bits, the check bits that are modified will identify the data bit that changed state. The error may be corrected by inverting the bit identified as being erroneous.
One common use of Hamming codes is to correct single bit errors within a group of data. Generally speaking, the number of check bits must be large enough such that 2kxe2x88x921 is greater than or equal to n+k where k is the number of check bits and n is the number of data bits. Accordingly, seven check bits are typically required to implement a single error correcting Hamming code for 64 data bits. A single error correcting Hamming code is capable of detecting and correcting a single error.
FIGS. 1-3 illustrate an example of a system employing a single-error correction (SEC) Hamming code. In this example, four data bits (D4, D3, D2, and D1) are protected using three check bits (P1, P2, and P3). The parity generator 10 (FIG. 1) is used to encode the data block that contains the data bits and the check bits. The encoding process is performed prior to storing or communicating the data. FIG. 2 shows an assignment of data bits to calculate the check bits. In this example, the check bit P1 is generated by an XOR (exclusive OR) of the binary values in D4, D3, and D1. Similarly, the check bit P2 is generated by an XOR of the binary values in D4, D2, and D1, and the check bit P3 is generated by an XOR of the binary values in D3, D2 and D1. FIG. 3 shows the bit positions and the corresponding content of these positions within the encoded data block. The data block, which includes the data bits and the generated check bits, may then be stored in a memory chip or communicated over a data communication path.
At the point of receipt, the data block is retrieved and decoded. The decoding process involves performing a validity check on the received word, and executing an error correction technique if an error was detected. To check whether an error occurred in the storage (or transmission) of the data block, the check bits P1, P2, and P3 are effectively regenerated using the received data, and each regenerated check bit is XORed with the corresponding received check bit to generate a corresponding syndrome bit. FIG. 4 is a table depicting a manner in which these syndrome bits may be generated. More particularly, syndrome bit S1 may be generated by XORing the received binary values in P1, D4, D3, and D1. If none of the received data bits (D4, D3, D1) is erroneous, the value of the received check bit P1 is effectively XORed with itself, and the syndrome bit S1 will be 0 (assuming the original check bit P1 is not erroneous). If one of the data bits (D4, D3, D1) or the check bit P1 is erroneous, the syndrome bit S1 will be 1 (asserted), thus indicating an error. Syndrome bits S2 and S3 may be generated similarly. Taken collectively, the syndrome bits S1, S2 and S3 may be used to identify the location of an erroneous bit. For example, the binary value of the syndrome bits in the order [S3, S2, S1] indicates the position of the erroneous bit within the 7 bit data block as depicted in FIG. 3. If the syndrome code is all zeros (i.e. xe2x80x9c000xe2x80x9d), the data has no single bit error. Upon identification of the erroneous bit position, the error is corrected by inverting the binary value in that position, i.e. from 0 to 1 or from 1 to 0.
It is a common practice to store data in, or communicate data through, multiple components. For example, a data block may be stored in a plurality of memory chips, or it may be communicated through a plurality of wires. An error may be introduced if one of the components is faulty. A Hamming code such as that described above may be used to address error correction in such systems.
For example, consider the case of storing D bits of data that are protected by C check bits using M memory chips. The data block therefore contains D+C bits. If the data block is to be evenly divided among the M memory chips, each memory chip will store X of the data and/or check bits of the data block, where X=(D+C)/M. The standard approach to providing error correction for chip failures is to divide the D+C data and check bits into X logical groups each including M bits, and assigning 1 bit from each chip to each of the groups. The check bits in each group form a SEC (single-error correcting) code such as a Hamming code. When any chip fails, it introduces at most one error into each group, and these errors are corrected independently using the SEC codes. If a Hamming code is used in each group, a total of C=X*L check bits are required, where L is the smallest integer such that 2L greater than M. This standard approach is inefficient because each group is able to independently identify which bit (if any) within the group is in error. However, if the only failures considered are memory chip failures, the failures in different groups are highly correlated.
It would be desirable to provide a system and method which allow for the reliable storage or transmission of data in environments wherein component failures are possible. In particular, it would be desirable to provide a system and method which allows errors in data to be detected and corrected while reducing the number of check bits which must be transmitted or stored. It would further be desirable to provide a simple mechanism for decoding the set of check bits to thereby identify a position of one or more bit errors due to, for example, a faulty component.
The problems outlined above may in large part be solved by a mechanism for decoding linearly-shifted codes for detecting and correcting errors in a data block in accordance with the present invention. In one embodiment, the mechanism is used in conjunction with a system which employs a check bits generation unit that receives and encodes data to be protected. The check bits generation unit effectively partitions the data into a plurality of logical groups. The check bits generation unit generates a parity bit for each of the logical groups, and additionally generates a global error correction.
The global error correction code is indicative of a predetermined combination of a set of error correction codes each individually associated with a corresponding logical group. In various embodiments, the global error correction code is equivalent to the result of generating individual error correction codes for each logical group and combining them in a predetermined manner.
In one particular embodiment, the data is divided into a total of X logical groups. The global error correction code may be equivalent to the result of (or may be derived by) shifting the error correction code for a given ith group by i bit positions, wherein i=0 to Xxe2x88x921, and by XORing corresponding columns of the resulting shifted error correction codes together. The global error correction code, which in this case is referred to as having xe2x80x9ctwisted checkxe2x80x9d bits (by virtue of the selective shifting of the individual error correction codes), thus includes a separate bit indicating the parity for each aligned column formed by the collection of resulting shifted error correction codes. The data along with the parity bit for each logical group and the global error correction code are then conveyed through a communication channel or are stored in memory.
An error correction unit including the mechanism for decoding the linearly-shifted codes is coupled to receive the plurality of data bits and the check bits following storage or transmission. The error correction unit is configured to generate a parity error bit for each of the logical groups of data based on the received data bits. The error correction unit may further be configured to generate a regenerated global error correction code in the same manner in which the original global error correction code is derived. Thus, in one embodiment, the regenerated global error correction code is equivalent to the result of (or may be derived by) shifting the regenerated error correction code for a given ith group by i bit positions, wherein i=0 to Xxe2x88x921, and by XORing corresponding columns of the resulting shifted error correction codes together.
A global syndrome code may be generated by XORing the original global error correction code with the regenerated global error correction code. This global syndrome code is indicative of a difference between the original global error correction code and the regenerated global error correction code.
The mechanism for decoding the linear shifted codes employs two shift registers, each cell of which contains a single bit. The shift registers are independently controlled by an associated control unit. In one particular embodiment, when a shift register is controlled such that its contents are shifted, the content of each cell is shifted one position to the right, the value in the right-most cell is discarded, and a logical low value (or xe2x80x9c0xe2x80x9d) is loaded into the left-most cell. Initially, the received parity bits are stored in a first shift register and the global syndrome bits are stored in a second shift register. While the right-most cell in the first shift register contains a logical xe2x80x9c0xe2x80x9d, both shift registers are shifted right one position. When the right-most cell of the first shift register contains a xe2x80x9c1xe2x80x9d, the content of the right-most cell of the second shift register is recorded as a first bit of a syndrome code which identifies the position of an error with any groups with an error. If the value recorded is a xe2x80x9c1xe2x80x9d, a bit-wise exclusive OR operation is then performed on the values in the first and second shift registers, and the result is stored in the second shift register. Subsequently, the contents of the second shift register are shifted by one position. Similar to the previous operation, the content of the right-most cell of the second shift register is again recorded, this time as the next bit of the syndrome code. A bit-wise exclusive OR is again conditionally performed upon the values in the first and second shift registers depending upon whether the last recorded bit was a xe2x80x9c1xe2x80x9d (and the result is stored in the second shift register), and the contents of the second shift register are shifted. These steps are repeated until all L bits of the syndrome code identifying a failed component have been recorded (where L is the smallest integer such that 2L greater than =M, where M is the number of components used).
Advantageously, the mechanism for decoding the linearly shifted codes is relatively simple in comparison to other potential solutions for decoding received check bits, such as techniques using Gaussian Elimination, which typically involve complex procedures.